en.wikipedia.org/wiki/Branch_predictor

The statement says all static-prediction decisions are made at compile time, but authoritative sources describe hardware static prediction as well.

• Intel’s optimization manual states that when there is no dynamic-branch-history entry, “the static predictor makes a prediction based on the direction of the branch.” That is a hardware decision made at run time, not at compile time.
• A classic branch-prediction paper likewise says “Static branch prediction can also be done with simple hardware such as prediction using branch direction (backward taken, forward not taken).”

So while some static prediction is indeed compile-time/compiler-driven, it is incorrect to say that all static prediction decisions are made at compile time.

Current high-end branch-prediction literature does not support the claim that most state-of-the-art predictors are using a perceptron predictor.

Evidence points the other way:

1. The BOOM processor documentation explicitly describes TAGE as a “state-of-the-art global history predictor.”
2. A MICRO 2020 paper states even more strongly that “All state-of-the-art branch predictors are variants of TAGE.”
3. The branch-prediction competition cited in the article did not establish perceptrons as the dominant state of the art: INRIA’s report on the 2016 Championship Branch Prediction competition says the PACAP team’s TAGE-SC-L and MTAGE-SC predictors won the three tracks of the competition.

Perceptron-based predictors are an important line of research, and some modern predictors use neural/perceptron components or hybrids. But the sentence as written is inaccurate because it presents perceptrons as the predominant state-of-the-art approach, whereas authoritative sources describe TAGE/TAGE-derived predictors as the main state-of-the-art baseline and competition winners.

The problem is the AMD part of the sentence. Infinity Fabric is AMD’s interconnect technology, not the CPU branch predictor.

• AMD’s own materials describe Infinity Fabric as a “system-wide interconnect” and as the technology by which dies/chiplets “interconnect with each other.”
• By contrast, Samsung’s Exynos M1 documentation explicitly describes its branch prediction as “Neural Net based predictor.”

So the sentence is misleading because it treats AMD Ryzen’s Infinity Fabric as though it were the branch-prediction mechanism. Even if a Ryzen core were to use a neural predictor, that would be a property of the core’s front-end/branch predictor, not of Infinity Fabric.