en.wikipedia.org/wiki/Systolic_array
1 correction found
An iWarp system has a linear array processor connected by data buses going in both directions.
iWarp systems were not linear arrays. Carnegie Mellon's own project page describes iWarp systems as n×m torus configurations, with a typical 8×8 torus.
Full reasoning
This sentence misdescribes the topology of iWarp systems.
Carnegie Mellon's archived iWarp Project Home Page says the supported parallel system configurations ranged from 4 cells up to 1024 cells in n × m torus configurations, and that a typical system was a 64-cell, 8×8 torus. A torus is a 2-dimensional network, not a linear array.
A second source describing historical interconnects likewise lists Intel/CMU iWarp as a 2D bidirectional torus. That directly contradicts the article's statement that an iWarp system was a linear array processor.
So the sentence should describe iWarp as a torus-connected parallel system, not as a linear array.
2 sources
- iWarp Project Home Page
Parallel system configurations: 4 cells up to 1024 cells in n x m torus configurations. Typical system: 64 cells, 8x8 torus, 1.2 GFlop/s peak.
- University dissertation discussing parallel interconnects
... ring), 2D bidirectional torus (Intel/CMU iWarp), 3D bidirectional torus ...