en.wikipedia.org/wiki/Computer_architecture
2 corrections found
The "instruction" in the standard measurements is not a count of the ISA's machine-language instructions, but a unit of measurement, usually based on the speed of the VAX computer architecture.
This confuses IPC with older MIPS-style benchmark units. In IPC, the “instruction” is the processor’s actual retired machine instructions per clock cycle, not a VAX-based normalized unit.
Full reasoning
The surrounding paragraph is about IPC (instructions per cycle), but this sentence describes something else.
Intel’s own performance documentation defines IPC simply as “Instructions per cycle” and separately defines INST as the “Number of instructions retired.” AMD’s profiling documentation likewise defines IPC as the average number of instructions retired per CPU cycle. That means the “instruction” in IPC is the processor’s actual executed/retired instruction stream, not a synthetic unit.
The part about a unit “based on the speed of the VAX computer architecture” refers to older MIPS / VAX MIPS / Dhrystone MIPS conventions, not to IPC. So this sentence is mixing up two different performance metrics.
In short: IPC = retired instructions per cycle; VAX-based normalized units = a different historical metric.
3 sources
- PCM Column Names Decoder Ring
IPC Instructions per cycle. This measures how effectively you are using the core. ... INST Number of instructions retired.
- Performance Metrics for AMD EPYC Zen 4 and later Core Architecture Processors
IPC (Sys + User): Instructions Per Cycle (IPC) is the average number of instructions retired per CPU cycle.
- An overview of common benchmarks
This is based on computer folklore saying that for typical programs a VAX 11/780 performs one million instructions per second. For comparisons across different instruction-set architectures, the unit MIPS ... has lost nearly all its significance.
Interrupt latency is the guaranteed maximum response time of the system to an electronic event (like when the disk drive finishes moving some data).
This misdefines interrupt latency. It is the delay from an interrupt request to the start of the interrupt handler, while having a guaranteed or bounded worst case is a separate property of some systems.
Full reasoning
Authoritative architecture and OS documentation defines interrupt latency as the delay between an interrupt request being raised/generated and the processor beginning to execute or service the interrupt handler.
- Apple’s kernel documentation: “Interrupt latency refers to the delay between an interrupt being generated and an interrupt handler actually beginning to service that interrupt.”
- Arm’s Cortex-M documentation similarly defines it as the number of cycles from the interrupt request to the first instruction of the interrupt handler.
So the article’s wording is incorrect in two ways:
- It defines interrupt latency as a system response time, rather than the delay to start handling the interrupt.
- It says this value is the guaranteed maximum response time. A bounded or guaranteed worst-case latency is a property some real-time systems aim to provide, but it is not the definition of interrupt latency itself.
In other words, interrupt latency is the time to begin servicing the interrupt, not a guaranteed maximum for the whole system’s response to an event.
2 sources
- Performance Considerations
Interrupt latency refers to the delay between an interrupt being generated and an interrupt handler actually beginning to service that interrupt. ... the interrupt latency caused by every device driver must be both small and bounded.
- A Beginner's Guide on Interrupt Latency - and Interrupt Latency of the Arm Cortex-M processors
The term interrupt latency refers to the number of clock cycles required for a processor to respond to an interrupt request ... between the assertion of the interrupt request up to the cycle where the first instruction of the interrupt handler expected.