All corrections
Wikipedia July 20, 2026 at 02:23 AM

en.wikipedia.org/wiki/Intel_MCS-48

3 corrections found

1
Claim
2× 8-bit timers
Correction

The 8748 and 8749 had one 8-bit timer/event counter, not two.

Full reasoning

Intel's own datasheets and user manuals describe the 8748/8749 MCS-48 family as having an 8-bit timer/counter or an 8-bit timer/event counter—singular. I could not find an Intel source describing these parts as having two 8-bit timers. So this table entry is incorrect on the timer count.

2 sources
  • MCS-48 Microcomputer User's Manual July 1977 98-270B

    The Intel 8048/8748/8035 is a totally self-sufficient 8-bit parallel computer ... The 8048 contains a 1Kx8 program memory, a 64 x 8 RAM data memory, 27 I/O lines, and an 8-bit timer/counter ...

  • intel®P8748H/P8749H

    The family contains 27 I/O lines, an 8-bit timer/counter, and on-board oscillator/clock circuits.

2
Claim
27 I/O ports
Correction

The 8049 had 27 I/O lines, not 27 separate I/O ports.

Full reasoning

Intel's own MCS-48 documentation describes the 8049 as having 27 I/O lines and one 8-bit timer/counter. That means the article's wording here is off by a lot: it is not 27 ports, but 27 individual I/O lines/pins. Intel manuals consistently use the singular phrase "27 I/O lines" for the 8049 family.

2 sources
3
Claim
27× I/O ports
Correction

These MCS-48 parts were specified with 27 I/O lines, not 27 I/O ports.

Full reasoning

Intel documentation for the MCS-48 family describes these chips as having 27 I/O lines. Calling them "27 I/O ports" is incorrect terminology and overstates the interface count: the devices do not provide 27 separate ports.

2 sources
Model: OPENAI_GPT_5 Prompt: v1.16.0